I am a Senior Engineer in Performance Architecture at Samsung Semiconductor in San Jose, California. I work on our hardware performance simulator, and I study how trends in large language models (LLMs) change hardware metrics, so that those trends can drive architectural decisions for next-generation AI inference hardware.

My work spans computer architecture, memory systems, and hardware/software co-design, applied to AI inference and privacy-preserving computing.

Before Samsung, I was a Scientist at Duality Technologies (2024–2026). There I designed and implemented components of TREBUCHET, a $15M DARPA DPRIVE effort (2021–2025) that built a custom 12 nm fully homomorphic encryption (FHE) accelerator ASIC for encrypted machine and deep learning, and I was Technical Lead for ARPA-H SHARE (Sharing Data for Rapid Collaboration on Encrypted Data), a privacy-preserving platform for healthcare collaboration built with ICF and Dana-Farber Cancer Institute.

I received my Ph.D. in Computer Science from the University of Utah in 2024, advised by Prof. Rajeev Balasubramonian in the Utah Arch Research Group. My thesis was on accelerating modern cryptography, with a focus on data movement. During my Ph.D. I was a research co-op at NVIDIA Research (2022) and AMD Research (2020). I received my B.Tech. from IIT Gandhinagar in 2017.

Service

• Technical Program Committee: IEEE/ACM ISCA 2027, IEEE/ACM MICRO 2026, IEEE/ACM ISCA 2026, IEEE HPCA 2026, IEEE ISPASS 2026, IEEE Micro 2022
• Founding Member and Steering Committee Member, Computer Architecture Student Association (CASA), 2020–2022
• Teaching Mentor, University of Utah: CS/ECE 6810 Computer Architecture; CS 3810 Computer Organization

News

• Sep 2026 Joined Samsung Semiconductor in San Jose as a Senior Engineer, Performance Architecture.
• 2026 Served on the Technical Program Committees of IEEE HPCA 2026, IEEE ISPASS 2026, IEEE/ACM ISCA 2026 and IEEE/ACM MICRO 2026; joined the IEEE/ACM ISCA 2027 Technical Program Committee.
• Mar 2025 Our paper “Accelerating FHE to Enable Privacy-Preserving Deep Learning” (Duality Technologies, USC ISI and NYU) appeared at GOMACTech 2025, the U.S. Government Microcircuit Applications & Critical Technology Conference.
• Jul 2024 Joined Duality Technologies as a Scientist, working on TREBUCHET, a 12 nm FHE accelerator ASIC under DARPA DPRIVE.
• Jun 2024 Received my Ph.D. in Computer Science from the University of Utah.
• May 2024 “Hyena: Balancing Packing, Reuse, and Rotations for Encrypted Inference” appeared at the IEEE Symposium on Security and Privacy (S&P) 2024.
• Mar 2023 “HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy” published in ACM Transactions on Architecture and Code Optimization.
• Feb 2023 “XCRYPT: Accelerating Lattice Based Cryptography with Memristor Crossbar Arrays” published in IEEE Micro.
• May 2022 Joined NVIDIA Research as Co-op. Project: Homomorphic Encryption at Modern GPU Datacenter Scale. Manager: Steve Keckler
• Apr 2022 Our work on Homomorphic Encryption based CNN inference EPIC: Efficient Packing for Inference using Cheetah appeared at the 6th Workshop on Cognitive Architectures, hosted in conjunction with HPCA 2022.
• Dec 2021 Our team has been selected as one of the finalists for Samsung’s Open Innovation Contest for AxDIMM Technology.
• Oct 2021 Our paper “CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration” appeared at HPCA 2022.
• Feb 2021 Blog post - Post Quantum Cryptography, SigArch Computer Architecture Today
• Nov 2020 Started collaboration with Prof. Elaine Shi (CMU) and Xiong Fan (Rutgers University) on project Acceleration of Post Quantum Cryptography
• Oct 2020 Started collaboration with Siddhartha Chhabra (Intel) on project Efficient Memory Integrity Verification
• Oct 2020 CASA, a student support group initiative for students (Founding member and Steering Committee), goes live!
• Aug 2020 Teaching Mentor for Fall 2020 CS/ECE 6810 Computer Architecture
• May 2020 Joined AMD Research as Co-op. Project: Processing-in-Memory. Manager: James Michael Allen Begole
• Nov 2019 Presented paper “Efficacy of Statistical Sampling on Contemporary Workloads: The Case of SPEC CPU2017” at IISWC 2019, in Orlando.
• Aug 2019 Started PhD at the University of Utah
• Apr 2019 Presented paper “Memory Centric Characterization and Analysis of SPEC CPU2017 Suite” at ICPE 2019, in Mumbai.
• Jan 2019 “PANE: Pluggable Asynchronous Network-on-Chip Simulator” published in ACM JETC. Simulator publicly available!
• Jan 2018 Joined IIT Gandhinagar (later Ashoka University) as Junior Research Fellow, under supervision of Prof. Manu Awasthi
• Aug 2017 Joined HCCI Hyderabad as Software Analyst.
• May 2017 Graduated with Bachelor of Technology from Indian Institute of Technology, Gandhinagar.