PANE : Pluggable Asynchronous Network-on-Chip Simulator
PANE, Pluggable Asynchronous Network-on-Chip, is a simulator that supports modeling and analysis of synchronous, asynchronous and mixed synchronous-asynchronous NoCs. It allows easy modeling for a variety of NoC designs with different topologies, routing algorithms, allocation and arbitration mechanisms, buffering schemes and workloads. PANE’s design allows for simulation of separate, yet interacting implementations of the data, routing-control and timing-control paths of the NoC. Full paper listed under Publications.
PANE code is available here. If you use PANE in your research, we would appreciate a citation to “Sneha N Ved, Sarabjeet Singh, Joycee Mekie, “PANE: Pluggable Asynchronous Network-on-Chip Simulator”, ACM Journal on Emerging Technologies in Computing Systems (JETC)”.
SPEC CPU 2017 Pinballs and Simulation Points
Whole and Regional Pinballs containing reproducible traces of Simulation points of SPEC CPU2017 benchmarks. Methodology described in the paper. Please contact me for a copy of the traces. If you do use these traces in your research, we would appreciate a citation to “Singh, Sarabjeet, and Manu Awasthi. “Efficacy of statistical sampling on contemporary workloads: The case of SPEC CPU2017.” 2019 IEEE International Symposium on Workload Characterization (IISWC). IEEE, 2019”.